The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 2000-51126, filed on Aug. 31, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention generally relates to testing of semiconductor integrated circuit devices. More specifically, the present invention is directed to a semiconductor integrated circuit into which test points are inserted to enhance testability and to minimize overhead caused by an increase in the number of input/output terminals.
2. Description of the Related Art
Recently, integration level and complexity of very large scaled integrated (VLSI) circuits has greatly increased with continuous development in design and processing technologies thereof. Therefore, a test to secure perfect operation of a completed system has become more important, as well as to secure a perfect design to meet specification requirements. This leads to a great increase in cost of a test to check whether a completed VLSI system is operable.
As a manner of easily testing a circuit from a design stage, a design for testability (DFT) has recently been introduced and applied. In a DFT, a given circuit is changed or redundant hardware is added to achieve easy testing. Test points are inserted to enhance controllability and observability, which are main factors of testability. The controllability is a degree of difficulty in changing a specific terminal (e.g., an output terminal of a specific gate) in a circuit to provide a specific signal by controlling a primary input value of the circuit. The observability is a degree of difficulty in observing a signal value set in a specific terminal in a circuit by controlling a primary input value of the circuit. The controllability and observability are combined to define the testability.
Generally, test points (TP) are classified into two types of test points, referred to as control points (CP) and observation points (OP). Control points are primary inputs (PI) used to enhance controllability and observation points are primary outputs used to enhance observability.
In order to improve testability, a test point insertion method enables a corresponding node to be accessible directly or indirectly from a primary input terminal or a primary output terminal. The test point insertion method conventionally applies manners of adding a pin, sharing a pin, adding a dedicated scan cell, using an exclusive-OR tree, and using a linear feedback shift register/multiple input signature register (LFSRfMISR).
The test point insertion method of adding a pin is disclosed in a paper xe2x80x9cRP-SYN: Synthesis of Random Pattern Testable Circuits with Test Point Insertionxe2x80x9d, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 8, pp. 1202-1213, August 1999, N. A. Touba and E. J. McCluskey et al. The test point insertion method of sharing a pin is disclosed in a paper xe2x80x9cCombining Multiple DFT Schemes with Test Generationxe2x80x9d, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 6, pp. 685-696, June 1999, B. Mathew and D. G. Saab. In this method, some of the additional pins required to be added can be shared with existing circuits. Even though an increase in the number of pins is determined by the number of select signals, the number of sharable pins is restricted. When inserting control points (CPs), if the number of sharable input pins is low, a number of CPs are shared using one input pin. Nevertheless, testability of the circuit is not completely improved. When inserting observation points (OPs), if the number of OPs is higher than that of the sharable output pins, an n-to-1 multiplexer (here, xe2x80x9cnxe2x80x9d is an integer of 3 or greater) can be used instead of a 2-to-1 multiplexer. Unfortunately, select signals for allocating input pins increases in number.
The test point insertion method of adding a dedicated scan cell is disclosed in a paper xe2x80x9cTest Point Insertion Based on Path Tracingxe2x80x9d, Proceedings of the 14th VLSI Test Symposium, pp. 2-8, 1996, M. A. Touba and E. J. McCluskey. In this method, control points (CPs) are inserted using a multiplexer, an OR-type gate, an AND-type gate, and a dedicated scan cell. An existing scan chain increases length in proportion to the number of test points (i.e., inserted cells), thus increasing a time required for a scan shift operation in a test vector. Therefore, a total test time is considerably increased. Further, cells are added to thus increase chip area and power consumption.
The test point insertion method of using an exclusive-OR tree is disclosed in a paper xe2x80x9cAn Observability Enhancement Approach for Improved Testability and At-Speed Testxe2x80x9d, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 8, pp. 1051-1056, August 1994, E. M. Rudnick et. al. The exclusive-OR tree has a tree structure until, after a plurality of observation points are connected to an input terminal of one exclusive-OR gate, output terminals thereof are sequentially connected to another exclusive-OR gate and are outputted to one output pin. Because of the plural observation points, the exclusive-OR gate tree must be constructed in many steps. This leads to an increase in gate count. If a fault effect is transferred from two observation points or more, the observation points are offset, so that there is a good chance of the observation points not being observed. Consequently, the observability cannot be perfectly improved. Also, the added exclusive-OR gates can deteriorate an efficiency of an automatic test pattern generator (ATPG).
The test point insertion method of using the LFSR/MISR is disclosed in a paper xe2x80x9cEfficient Test-Point Selection for Scan-based BISTxe2x80x9d, IEEE Trans. on Computer-Aided Design of Integration circuits and System, Vol. 6, No. 4, pp. 67-676, December 1998, H. C. Tsai et al., and in U.S. Pat. No. 5,737,340 entitled xe2x80x9cMULTI-PHASE TEST POINT INSERTION FOR BUILT-IN SELF TEST OF INTEGRATED CIRCUITSxe2x80x9d, April 1998, Tamarapalli et al. The LFSR/MISR are mainly used as a pattern generator and a response analyzer in a built-in self test (BIST) circuit, respectively. Also, the LFSR/MISR can be used in the test point insertion. If the number of test points is great, the foregoing method generally has as a shortcoming increasing overhead with respect to area and power consumption.
Even though various test point insertion methods have been used for enhancing testability of semiconductor integrated circuits, conventional methods have shortcomings such as increasing pin overhead, increasing area overhead, increasing power consumption, increasing test time, and restrictive enhancement of the testability.
The present invention is therefore directed to testing of integrated circuits, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
Thus, an object of the present invention is to provide a semiconductor integrated circuit capable of enhancing testability and minimizing overhead without performance deterioration, and minimizing an increase in area required in connection with a test point insertion method.
In accordance with one aspect of the invention, a semiconductor integrated circuit device includes a logic circuit having one or more observation points and a control point. A data transfer unit includes a plurality of scan cells that are coupled to the logic circuit. A first selection unit selects one of normal data supplied from the logic circuit or data supplied from the one or more observation points, and outputs the selected data to the data transfer unit. A second selection unit outputs one of the normal data and one of scan data transferred from the data transfer unit, to the control point.
In accordance with another aspect of the invention, a semiconductor integrated circuit device includes a logic circuit having one or more observation points and a control point. A first data transfer unit includes a plurality of scan cells that are coupled to the logic circuit. A second data transfer unit includes a plurality of scan cells that are serially coupled to the first data transfer unit. A first selection unit selects one of normal data supplied from the logic circuit and data supplied from the one or more observation points, and outputs the selected data to the first data transfer unit. A second selection unit outputs one of the normal data and one or more scan data transferred from the second data transfer unit, to the control point.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.